Cadence Recruitment 2022 | Freshers | Design Engineer | B.Tech/ M.Tech – ECE/ EEE | 2020-2022 Batch | Bangalore
Company: Cadence Design Systems
Cadence Recruitment 2022: Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Company Website: www.cadence.com
Positions: Design Engineer
Experience: Freshers (0-2 years)
Job Location: Bangalore
Salary: Best in Industry
Eligibility Criteria for Cadence Recruitment 2022:
- 0-1 years (with Btech) or 0-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
- Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, ethernet, SRIO, JESD204, DDRIO etc is MANDATORY
- Hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc is MANDATORY
- Candidates are expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.
- 0-2 years of experience in FPGA Design, PCB schematic and layout design & Prototyping will be an added plus
- Pre-Silicon IP/SoC Physical Layer Electrical Validation experience related to board bring-up & Debug is an added plus.
- Familiarity with Verilog RTL coding, FPGA coding, Labview, python, C/C++, TCL is an added plus
We have an immediate opening in the Post Silicon Physical Layer Electrical Validation team at Cadence Design Systems Bangalore, for the post of “Lead Design Engineer
The responsibility entails performing pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation primarily on Cadence’s High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.
How to Apply for Cadence Recruitment 2022?
Interested and Eligible candidates can apply this drive in online as soon as possible
Apply Link: Click Here