Synopsys Off Campus Drive 2023 | Freshers | Analog Design Engineer | BE/ B.Tech/ ME/ M.Tech – ECE/ EEE | 2020 – 2022 Batch | Noida
Company: Synopsys India
Synopsys Off Campus Drive 2023: Synopsys India established its operations in Bangalore as an offshore R&D center in 1995 and added a field organization in 1997. Today, the company has offices in Hyderabad, Noida, Mumbai and New Delhi, where more than 1,300 employees are involved in the research, design and development of key technologies and products that accelerate innovation in the global electronics market.
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing.
Company Website: www.synopsys.com
Positions: Analog Design Engineer I
Salary: Best In Industry
Job Location: Noida
Experience: Freshers (0-2 years)
Eligibility Criteria for Synopsys Off Campus Drive 2023:
- BE with 0-2 years of relevant experience / M.Tech 0-1 years of relevant experience in Electrical/ Electronics/ VLSI Engineering or other relevant fields of study.
- Internship of 0.5-1 Year in Analog and Digital design in any competent organization.
- Fresh BE/ B.TECH/ ME/ M.TECH with good Academics in Electrical/ Electronics/ VLSI Engineering or another relevant field of study.
- CMOS Analog circuit design fundamentals, device physics, basic understanding of layout and parasitic extraction, differential amplifiers, current mirrors etc.
- Strong Digital Electronics Basics.
- Knowhow of RLC circuits, basic knowhow of PLL, voltage regulators, Bangap references, Control systems etc.
We’re looking for a Senior Analog Design Engineer to join the team. Does this sound like a good role for you? This role involves analyzing various mixed-signal techniques for dynamic and static power reduction, performance enhancement and area reduction. You’d leverage your strong understanding of circuit simulation and circuit layout as well as knowledge of bipolar, CMOS, passive structure, and interconnect failure modes. You will be part of a strong development team in the area of High-Speed PHYSICAL Interface Development. You will develop Analog Full custom circuit macros, i.e., PLL, Regulators, equalizers, Analog Front End, needed for High Speed PHY IP, in planer and fin-fet CMOS technology.. You will be working with experienced teams locally and with people from various sites spread across the globe
How to Apply for Synopsys Off Campus Drive 2023?
Eligible candidates may apply through online mode ASAP.
Apply Links: Click Here