Google India Recruitment 2020 | DFT CAD Engineer | BE/ B.Tech – Electrical/ Electronics Engineering | Bangalore
Company: Google India Pvt Ltd
Google Inc. is an American multinational technology company specializing in Internet-related services and products. These include online advertising technologies, search, cloud computing, and software. Most of its profits are derived from AdWords, an online advertising service that places advertising near the list of search results.
Google was founded by Larry Page and Sergey Brin while they were Ph.D. students at Stanford University. Together they own about 14 percent of its shares but control 56 percent of the stockholder voting power through supervoting stock. They incorporated Google as a privately held company on September 4, 1998.
Website: www.google.com
Position: DFT CAD Engineer
Job Location: Bangalore
Experience: 4 Years
Salary: Best In Industry
Education: Bachelor’s degree in Electrical Engineering or equivalent practical experience.
Preferred qualifications:
- Experience with design tools like Tessent MBIST, Spyglass DFT, Design Compiler, VCS/NCSIM.
- Experience in DFT methodologies in 7nm – 40nm process nodes.
- Experience with MBIST, Scan, ATPG, Simulations, Spyglass DFT and STA.
- Experience and/or knowledge in hierarchical DFT flows, and IP integration (SRAM, IO, hardened digital IP and analog IP).
- Experience leading one or more aspects of design for test flow/methodology to successful tape-outs.
Responsibilities:
- Collaborate with DFT teams to come up with DFT specifications and implementation plans for Application Specific Integrated Circuits utilising DFT tools and methodologies for internal and external IP
- Plan and implement tool flows to meet test requirements for high volume manufacturing, including at-speed scan test with compression, Logic BIST, Memory BIST, and boundary scan, while utilizing industry standards
- Create tools/flows and methods to enable Implementation, integration and verification of DFT logic designs at block/IP level and chip level while minimizing DFT impact on schedule, timing, area, and power
- Create flows/methods to enable timing constraints for all DFT modes and collaborate with physical design teams to close timing and physical design signoff requirements.
- Enable automation to generate production quality manufacturing test patterns, and assist with bring-up and debug on Automated Test Equipment (ATE)
Application Link: Link Expired
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