ARM® Recruitment 2017 | Freshers | Graduate Engineer | BE/ B.Tech/ ME/ M.Tech | 2016 & 2017 Batch | Bangalore | November 2017
Company: ARM®
ARM® is at the heart of the world’s most advanced digital products. Our technology enables the creation of new markets and transformation of industries and society. We design scalable, energy efficient-processors and related technologies to deliver the intelligence in applications ranging from sensors to servers, including smartphones, tablets, enterprise infrastructure and the Internet of Things.
Our innovative technology is licensed by ARM Partners who have shipped more than 50 billion Systems on Chip (SoCs) containing our intellectual property since the company began in 1990. Together with our Connected Community, we are breaking down barriers to innovation for developers, designers and engineers, ensuring a fast, reliable route to market for leading electronics companies.
Website: www.arm.com
Position: Graduate Engineer
Experience: 0 – 1 Year
Job Locations: Bangalore
Salary: Best In Industry
Eligibility Criteria:
- Bachelors or Master’s Degree in Electronics Engineering or equivalent
- 0-1 years of engineering experience in Verilog modelling and verification
Role Purpose:
The Physical IP Division inside ARM creates Physical IPs of various types like Standard Cells, Memory, and Interface which are extensively used by thousands of IC designers around the world to design leading edge chips. We are currently marketing and developing solutions from 180nm to 10nm and research work on 7nm solutions is happening at various ARM design centres worldwide.
A dedicated team of experienced professionals in software, methodology and flow development aids this process of creating Physical IPs for leading edge chips. Forming part of the ARM Physical IP Division, the Modelling and Methodologies Group develops Front end models for Standard Cells, Memory and Interface physical IP as well as creates methodologies to validate the physical IP. The front end model development involves creation of Simulation, ATPG, Low Power views which gets used during SoC IP validation. The group also focuses on developing methodologies like Correlation, Simulation, Synthesis, DFT, ATPG, Logic Equivalence, Place and Route etc. that makes the IP robust and high quality while reducing the cost with improved efficiency.
Characteristics & Requirements:
- Quick learner, good problem solving and debugging skills
- Willingness to be flexible and accept new challenges
- Capable of working as a team player or independently
- Good analytical and reasoning skills
- Enthusiastic and self-motivated
- Good communication skills
Essential Technical Experience:
- Good understanding of digital circuits fundamentals and SoC concepts
- Working knowledge of scripting tools (TCL, Perl)
Desirable Technical Experience:
- Experience with Verilog modelling and verification
- Experience with Frontend flows like Simulation, Synthesis, ATPG and Logic Equivalence
Application Link: Closed
